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Intel's upcoming transactional memory feature
Here is a
posting on the Intel software network describing the "transactional
synchronization extensions" feature to be found in the future "Haswell"
processor.
With transactional synchronization, the hardware can
determine dynamically whether threads need to serialize through
lock-protected critical sections, and perform serialization only when
required. This lets the processor expose and exploit concurrency that would
otherwise be hidden due to dynamically unnecessary synchronization. At the
lowest level with Intel TSX, programmer-specified code regions (also
referred to as transactional regions) are executed transactionally. If the
transactional execution completes successfully, then all memory operations
performed within the transactional region will appear to have occurred
instantaneously when viewed from other logical processors. A processor
makes architectural updates performed within the region visible to other
logical processors only on a successful commit, a process referred to as an
atomic commit.
Needless to say, there should be interesting ways to use such a feature in the kernel if it works well, but other projects (PyPy, for example) have also expressed interest in transactional memory.
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